What is Design-for-Test?

Testability is a design attribute that measures how easy it is to create a program to
comprehensively test a manufactured design’s quality. Traditionally, design and
test processes were kept separate, with test considered only at the end of the
design cycle. But in contemporary design flows, test merges with design much
earlier in the process, creating what is called a design-for-test (DFT) process flow.
Testable circuitry is both controllable and observable. In a testable design; setting
specific values on the primary inputs results in values on the primary outputs
which indicate whether or not the internal circuitry works properly. To ensure
maximum design testability, designers must employ special DFT techniques at
specific stages in the development process.

DFT Strategies
At the highest level, there are two main approaches to DFT: ad hoc and
structured. The following subsections discuss these DFT strategies.

Ad Hoc DFT
Ad hoc DFT implies using good design practices to enhance a design's testability,
without making major changes to the design style. Some ad hoc techniques
include:

• Minimizing redundant logic
• asynchronous logic
• clocks from the logic
• Adding internal control and observation points

Structured DFT

Structured DFT provides a more systematic and automatic approach to enhancing
design testability. Structured DFT’s goal is to increase the controllability and
observability of a circuit. Various methods exist for accomplishing this. The most
common is the scan design technique, which modifies the internal sequential
circuitry of the design. You can also use the Built-in Self-Test (BIST) method,
which inserts a device’s testing function within the device itself. Another method
is boundary scan, which increases board testability by adding circuitry to a chip.